The present invention relates to an electrically erasable and programmable read only memory (hereinafter referred to as EEPROM), more particularly, to an electrically page erasable and programmable read only memory device having a plurality of flash-type floating gate transistors.
The EEPROM is a read only memory which is electrically erasable and programmable owing to the electrical characteristics of EEPROM cells in an array. Floating gate tunnel oxide (FLOTOX) type transistors erased by exposure to ultraviolet light and flash-type floating gate transistors are all used as the EEPROM cells. The structure of the flash-type floating gate transistor is similar to the structure of the FLOTOX-type transistor in that it has a two-layer polysilicon gate but is dissimilar thereto in that the edges of the source region and the drain region overlap the floating gate which underlies the thin gate oxide layer.
The FLOTOX-type transistor used as the EEPROM cell is programmable in the manner of the tunneling of electrons which drift to the floating gate from the drain through an approximately 100 .ANG. tunnel oxide layer, and it is erasable in the manner of the tunneling of electrons which drift from the floating gate to the source through the approximately 100 .ANG. tunnel oxide layer.
A basic technology relating to the above mentioned FLOTOX-type transistor, is disclosed in U.S. Pat. No. 4,203,158 of Intel.
Referring now to an array using the FLOTOX-type transistors, since all of the drains are interconnected with a common bit line, high voltage is applied to all drains including unwanted drains. Therefore, another transistor called a selection transistor is used for selecting only the desired cells. Accordingly, in the EEPROM device which uses FLOTOX-type floating gate transistors as memory cells, two transistors are required for a bit or a cell, so that the manufacture of the high density integrated EEPROM device is difficult.
On the other hand, the flash-type floating gate transistor as described hereinabove has a structure in which the edges of a source region and a drain region overlap a floating gate with a thin tunnel oxide layer therebetween, as illustrated in FIGS. 1A to 1D.
FIG. 1A shows a plane view of the flash-type floating gate transistor. FIG. 1B and FIG. 1C are cross sectional views respectively taken along lines b--b' and c--c' of the FIG. 1A, and FIG. 1D is an equivalent circuit diagram. In FIG. 1A, a source diffusion region 52, the source region 54 and drain region 56, a floating gate 58 formed of polysilicon, a control gate 60 formed of polysilicon and a channel region 64 which is defined by the source region 54 and the drain region 56, are illustrated.
In FIG. 1B, a semiconductor substrate 50, the source diffusion region 52, the source region 54, the drain region 56, the control gate 60 formed of polysilicon, the floating gate 58 formed of polysilicon, the channel region 64, a tunnel oxide layer 62 between the channel region 64 and the floating gate 58, and an oxide dielectric layer 66 between the control gate 60 and the floating gate 58, are illustrated.
In FIG. 1C, the semiconductor substrate 50, the source diffusion region 52, the tunnel oxide layer 62, the control gate 60, the floating gate 58 and the oxide dielectric layer between the control gate 60 and the floating gate 58, are illustrated.
FIG. 1D is an equivalent circuit diagram of the flash-type floating gate transistor, wherein a capacitive coupling 70 between the control gate 60 and the floating gate 58, the capacitive coupling 76 between the floating gate 58 and the source region 54, the capacitive coupling 72 between the floating gate 58 and the drain region 56, and the capacitive coupling 74 between the floating gate 58 and the channel region 64, are illustrated.
Referring now to FIG. 1B, erasing, programming and reading operations of the EEPROM, which is composed of the flash-type floating gate transistors, will be described.
When the flash-type floating gate transistor is used for the memory cell, an erase line is connected to the source region 54, a bit line to the drain region 56, and a word line to the control gate 60.
The erasing operation of the EEPROM is achieved by increasing the potential of the source 54 (or the erase line) to 12 volts, earthing the control gate 60 (or the word line) and floating the drain 56 (or the bit line). With Fowler-Nordheim tunneling, electrons drift from the floating gate 58 to the source 54 through the tunnel oxide layer 62. At this time, the threshold voltage of the transistor is reduced to about 1-2 volts.
The programming operation is achieved by applying high voltage to the drain 56 of the cell. Practically, it is achieved by applying about 7 volts to the drain region 56 and 12 volts to the control gate 60, while hot electrons are generated in the depletion region which is between the drain 56 and the channel 64 and they are injected to the floating gate 58, this increases the threshold voltage of the transistor to 6-7 volts.
On the other hand, the reading operation is achieved by applying 5 volts to the control gate 60 and 1.5 volts to the drain region 56, and then by sensing channel current which flows to the source 54 from the drain 56 of a programmed cell or an erased cell.
When using such a flash-type floating gate transistor as stated above, only one transistor is needed in a bit, and all of the cells are erasable at one time, unlike the array using the FLOTOX-type transistors. Such an array of the EEPROM using the flash-type transistors as the cells is disclosed in U.S. Pat. No. 4,698,787 obtained by the Exel Microelectronics, Inc.
This patent is for the art by which memory cells in an array are erasable block by block or byte by byte. It is illustrated in FIG. 2, FIG. 3 and FIG. 4, wherein FIG. 2 is a schematic diagram of all memory cells of said patent, FIG. 3 is an inner circuit diagram of FIG. 2 when a block-erasable operation is carried out, and FIG. 4 is an inner circuit diagram of another embodiment of said patent when a byte-erasable operation is carried out.
Referring to a construction of the EEPROM chip of said patent illustrated in FIG. 2, pages PG.sub.1 -PG.sub.N are arranged in the left side of a row address decoder 81 positioned in the center of the chip and pages PG.sub.N+1 -PG.sub.2N are arranged in the right side of the row address decoder 81, and each of pages PG.sub.1 -PG.sub.2N owns a plurality of column lines, a plurality of word lines, and a plurality of the cells which are connected to those lines. The number of the cells are obtained by multiplying the number of the column lines and the number of the word lines.
The column lines of a page are connected in common to one of the input/output (I/O) lines of a column address decoder 83. When the number of the pages is 2n, the I/O lines of column address decoder 83 are 2n in number and are labeled I/O.sub.1,I/O.sub.2,...,I/O.sub.2N. At this time, I/O.sub.1 is connected to the common column line of PG.sub.1, I/O.sub.2 to the common column line of PG.sub.2, and I/O.sub.2N to the common column line of PG.sub.2N. The I/O lines from column address decoder 83 for column selection and a common erase line 11 for erasing operation are connected to all of the pages.
FIGS. 3 and 4 are embodiments of 2, representing the formation of an array of the memory cells. In FIGS. 3 and 4, for the convenience of description, the number of the I/O lines is eight.
The cells in the array illustrated in FIG. 3 are the EEPROM cells which are block-erasable. The control gates of the cells in a row are connected in common to the word line of the same row. The drains of the cells in a column are connected in common to the bit line (or I/O line) of the same column. The sources of the cells in a row are connected in common to the common source line of the same row. Since the erase line 11 is coupled in common to all of the common source lines CS.sub.1 -CS.sub.K, erasing voltage is applied to all of the common source lines CS.sub.1 -CS.sub.K through the erase line 11.
FIG. 4 shows an array of the EEPROM cells which is byte-erasable. The control gates of the cells in a row are connected in common to the word line of the same row. The drains of the cells in a column are connected in common to the bit line of the same column. The sources of the cells in a row are connected in common to the common source line of the same row. The array in FIG. 4 differs from the array in FIG. 3 in that the N-channel metal oxide semiconductor (NMOS) transistors which are positioned one by one in the right end of each row, are used for the byte-erasing operation. The sources of the NMOS transistors are connected respectively to the respective common source lines and the gates of the NMOS transistors are connected respectively to the respective word lines, while the drains of all the NMOS transistors are coupled in common to the erase line 11. That is, in the array of FIG. 3, as the erasing voltage through the erase line 11 is applied to all of the common source lines in a block, all of the cells in a block are erasing at one time. In the array of FIG. 4, however, since the erasing voltage through the erase line 11 is only applied to a selected common source line, only the cells in a row are erased at one time.
As the erasing operation is achieved by applying high voltage to the erase line 11 and by grounding all of the word lines, all of the memory cells of a chip are erased at one time, which causes unrequired cells to be erased. It is because when high voltage is applied to the erase line 11 in the erasing operation, the source 54 of FIG. 1B has been formed within the source diffusion region 52 of FIG. 1B with them not separated. Thus, erasing of all of the memory cells occurs at the same time. In this case, the access time of all memory cells will be delayed because resistance of corresponding grounding parts increases accordingly as the drain voltage controlling the access time of the memory cells increases. As it is difficult for all of the memory cells to be fabricated under the same conditions, the access times of all of the memory cells are not equal. In this case, the total time required to access all of the memory cells is determined by the longest access time. For example, when the access time of one of the memory cells is 100 ns and the access time of another memory cell is 140ns, the total time required to access two memory cells is 140ns.
Therefore, an increase of parasitic resistance due to the high density integration of memory device and the access time of the memory cells must be considered.